Search - Design Compiler

[ELanguage] mz

Description: 计算机专业编译原理课程设计编程只有代码-Computer Curriculum Design Compiler Principle only programming code
Platform: | Size: 15362 | Author: 周启伦 | Hits:

[CSharp] kka

Description: 计算机专业编译原理课程设计编程只有代码-Computer Curriculum Design Compiler Principle only programming code
Platform: | Size: 8678 | Author: 周启伦 | Hits:

[ELanguage] pl0_by_java

Description: 编译原理课程设计 PL0编译器 java版本-Course Design Compiler Principle PL0 java compiler version
Platform: | Size: 404717 | Author: bailm | Hits:

Description: 文件中包括电子琴、步进电机控制、电子钟等实用程序控制，已经通过了编译，适当设计编译环境、端口等相信会对该方面的朋友有帮助。-document include organ, stepper motor control, electronic bell practical programmed through a compiler, appropriate Design Compiler environment, ports, etc. I believe that the friends help.
Platform: | Size: 10484 | Author: 程承 | Hits:

[WEB Code] tomy

Description: 编译原理课程设计报告lr(1)文法中国出版社-Course Design Compiler Principle lr report (1) grammar Chinese publishers
Platform: | Size: 14112 | Author: 唐铭鸿 | Hits:

[Other resource] DesignCompiler

Description: Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
Platform: | Size: 1310370 | Author: qindao | Hits:

[CSharp] 22121128

Description: VC实现逆波兰表达式的转换，编译原理课程设计-VC reverse Polish expression conversion, the design compiler theory courses
Platform: | Size: 119313 | Author: 肖炜 | Hits:

[Other resource] hm

Description: /* 程序名称： LL(1)文法分析程序 */ /* 程序用途：编译原理课程设计 */ /* 编写日期： 2006年6月29日 */ /* 实验题目：识别下列表达式 */ /* E->E+T|E-T|T */ /* T->T*F|T/F|F */ /* F->(E)|i */ -/ * process Name : LL (1) grammar analysis program * / / * process uses : Course Design Compiler Principle * / / * prepare Date : June 29, 2006 * / / * experimental topics : identify the following expression * / / * E -
Platform: | Size: 4240 | Author: 黄铭 | Hits:

[ELanguage] B4

Description: 编译原理课程设计很珍贵的资源快来下载吧-Course Design Compiler Principle very precious resources Come download it! !
Platform: | Size: 37266 | Author: 123 | Hits:

[ELanguage] compilerPL

Description: 编译原理课程设计VC实现源码(可以运行）-Course Design Compiler Principle VC source (run)
Platform: | Size: 88223 | Author: fly | Hits:

[File Operate] cp%2E

Description: 编译原理课程设计报告对以下文法，采用算符优先分析算法，对G[S]所定义的赋值语句进行语法分析，并在语法分析过程中将所输入的扶植语句翻译为四元式。-Course Design Compiler Principle report on the following grammar, using operator priority analysis algorithm, G [S], as defined in the assignment syntax analysis, and the syntax analysis process will be supported by the input of the translation of the statement-four yuan.
Platform: | Size: 14809 | Author: zjd | Hits:

[Other resource] C_software

Description: c语言程序设计编译工具。turboc2.0的安装版本。可以解压然后安装/-c Language Program Design Compiler tool. Turboc2.0 version of the installation. Decompression can then install /
Platform: | Size: 6571092 | Author: 郭方 | Hits:

[OS program] C-compiler-design

Description: C-编译器的设计,有详细的文档 1. 具有比较友好的GUI界面（仿照了我自己正在用的emacs）； 2. 语法支持比较全面（毕竟是C-，语法还是不多的）； 3. Error Recovery； 4. 生成p-code，便于理解； 5. 生成asm代码，通过masm6.0基本都能编译成功，但代码没有优化，效率极低。-C-compiler design, is a detailed document. compared with a friendly GUI interface (modeled on my own is using the emacs); 2. Grammar supported the more comprehensive (after all, C-, grammar or less); 3. Error Recovery; 4. Generation p-code, easy to understand; 5. asm2 code generated by the basic masm6.0 able to successfully build, but code has not been optimized, extremely inefficient.
Platform: | Size: 996016 | Author: wangfei | Hits:

[Other resource] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113973 | Author: mingming | Hits:

[ELanguage] Complier_PL0

Description: 编译原理课程设计VC实现源码,以PL0语言做示例，适合初学者使用-Course Design Compiler Principle VC source to PL0 language exemplars, for beginners
Platform: | Size: 80494 | Author: sun | Hits:

[Other resource] HJFGF

Description: 黄金分割法的源代码用于优化设计 Turbo 2.0 下编译-0.618 method of optimizing the source code for Turbo Design Compiler 2.0
Platform: | Size: 1405 | Author: 李冰 | Hits:

[Develop Tools] synopsy_dc_ppt

Description: synopsys dc 中文ppt教材，比较详细! 可是SYnopsys公司培训的教材!难得的好东西!对学习Design compiler的人非常有帮助-synopsys dc Chinese ppt materials, more detail! But SYnopsys corporate training materials. rare good things! Design study of c ompiler are very helpful
Platform: | Size: 798353 | Author: 张华 | Hits:

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